STMicroelectronics is ramping up its PIC100 silicon photonics platform for high-volume data-center and AI-cluster interconnects. They’re leveraging 300 mm silicon wafers and edge-coupled Mach-Zehnder modulators to improve fiber-to-chip coupling.
The move, announced in early 2025, is now entering mass production at ST’s Grenoble facility. Surging hyperscaler demand and long-term capacity reservations—especially from Amazon Web Services (AWS)—are driving this push.
ST plans a multi-year capacity expansion that will more than quadruple PIC100 output by 2027. The roadmap also extends the platform with TSV-enabled connectivity to boost density, integration, and thermal efficiency.
The timing feels right, given the broader market shift toward silicon photonics. The industry’s chasing higher data throughput and lower power per bit in large-scale data centers and AI accelerators.
High-volume production of PIC100 on 300 mm wafers
ST’s PIC100 platform is moving into high-rate manufacturing on full-size 300 mm silicon wafers at its Grenoble, France campus. This is meant to deliver low-cost, high-volume optical interconnects for data centers and AI clusters.
The production approach focuses on edge-coupled Mach-Zehnder modulators. This design better matches fiber modes with silicon nitride waveguides and improves coupling efficiency and system reliability.
It’s all about supporting the scale needs of hyperscalers while keeping tight integration with existing silicon photonics ecosystems. AWS has played a key role in shaping the PIC100 architecture and its manufacturing cadence.
ST highlights its 300 mm production lines, which offer lower per-lane costs and higher throughput compared to smaller-diameter processes. They’re seeing a clear, long-term reservation pattern from large cloud operators, hinting at durable demand for silicon photonics-based interconnects as data-center scale keeps climbing.
- 300 mm wafer scale at Grenoble drives unit costs down and enables rapid capacity ramp
- Edge-coupled Mach-Zehnder modulators align fiber and chip modes for higher extinction and lower insertion loss
- Silicon nitride waveguides improve low-loss propagation and broad wavelength compatibility
- Strong AWS collaboration informs design choices and manufacturing cadence
Market growth and industry signals
ST cites market intelligence putting data-center pluggable optics at $15.5 billion in 2025, with forecasts topping $34 billion by 2030. CPO (co-packaged optics) could contribute more than $9 billion, showing a shift toward densely integrated packaging.
LightCounting’s projections, referenced by ST, suggest transceivers using silicon photonics modulators will jump from about 43% in 2025 to roughly 76% by 2030. That’s a pretty sharp transition to PIC-based solutions in data paths.
Manufacturers with scalable 300 mm platforms look well positioned to capture most of this growth. Hyperscalers keep reserving capacity far in advance, so the momentum’s definitely there.
TSV-enabled connectivity and density roadmap
Beyond the PIC100 baseline, ST is rolling out a through-silicon via (TSV) capability to boost optical connectivity density and module integration, while improving thermal performance. The PIC100-TSV roadmap supports near-packaged optics (NPO) and co-packaged optics (CPO) migration paths that hyperscalers are moving toward.
With ultra-short vertical electrical connections through TSVs, ST expects denser modules and the ability to push up to 400 Gb/s per lane. That could open up new levels of interconnect bandwidth in compact form factors.
- TSV integration increases optical connectivity density and module packing efficiency
- NPO and CPO migration paths align with hyperscaler deployment models
- Ultra-short vertical electrical connections enable higher per-lane data rates, up to 400 Gb/s
Upcoming showcase and industry context
ST plans to present the PIC100 platform at the Optical Fiber Conference in Los Angeles. They’ll highlight both the mature PIC100 product with edge-coupled modulators and the new PIC100-TSV features.
The company sees this event as a chance to show its ability to scale silicon photonics for data-center interconnects and AI cluster needs. They’re putting a spotlight on cost efficiencies and the thermal perks that come from using 300 mm wafer production.
Here is the source article for this story: STMicro ramps silicon photonics platform